verilog-generator
Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
Eriemon/verilog-generator
View on GitHub ↗Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
verilog-generator grew +7.4% in the last 30 days, ranks 1261st of 2,580 in Agent SDK / Framework, last commit 60 days ago.
Star trajectory
79 days tracked2026-08-07321 stars today2026-10-25
Momentum
+7.4% in 30d, above the Agent SDK / Framework median of +1.5%.
Maintenance
Last commit 60 days ago, staler than the median of 14d.
How it compares in Agent SDK / Framework
verilog-generator
321
stars
+7.4% 30d
commit 60 days ago
Agent SDK / Framework median
310
stars
+1.5% 30d
commit ~14d ago
Leader · rea
379.8k
stars
+91425.1% 30d
commit today
Ranked 1261st of 2,580 by stars.
fidetolabs/qanat322-1vinilana/jev-gateway322-1
Eriemon/verilog-generator321
AgenticMatrix/open-claude-code321+0ServiceNow/TapeAgents320+1- Language
- Python
- License
- Apache License 2.0
- Contributors
- 2
- Forks
- 23
- Watchers
- 4
- Open issues
- 0
- Releases
- 14
- Created
- 2026-05-08
- Stars this week
- +3
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